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? semiconductor components industries, llc, 2007 april, 2007 ? rev. 11 1 publication order number: ncp1216/d ncp1216, ncp1216a pwm current?mode controller for high?power universal off?line supplies housed in a soic?8 or pdip?7 package, the ncp1216 represents an enhanced version of ncp1200 based controllers. due to its high drive capability, ncp1216 drives large gate?charge mosfets, which together with internal ramp compensation and built?in frequency jittering, ease the design of modern ac?dc adapters. with an internal structure operating at different fixed frequencies, the controller supplies itself from the high?voltage rail, avoiding the need of an auxiliary winding. this feature naturally eases the designer task in some particular applications, e.g. battery chargers or tv sets. current?mode control also provides an excellent input audio susceptibility and inherent pulse?by?pulse control. internal ramp compensation easily prevents sub?harmonic oscillations from taking place in continuous conduction mode designs. when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so?called skip cycle mode and provides excellent efficiency at light loads. because this occurs at a user adjustable low peak current, no acoustic noise takes place. the ncp1216 features an efficient protective circuitry, which in presence of an over current condition disables the output pulses while the device enters a safe burst mode, trying to restart. once the default has gone, the device auto?recovers. features ? no auxiliary winding operation ? current?mode control with adjustable skip?cycle capability ? internal ramp compensation ? limited duty cycle to 50% (ncp1216a only) ? internal 1.0 ms soft?start (ncp1216a only) ? built?in frequency jittering for better emi signature ? auto?recovery internal output short?circuit protection ? extremely low no?load standby power ? 500 ma peak current capability ? fixed frequency versions at 65 khz, 100 khz, 133 khz ? internal temperature shutdown ? direct optocoupler connection ? spice models available for transient and ac analysis ? pin?to?pin compatible with ncp1200 series ? pb?free packages are available typical applications ? high power ac?dc converters for tvs, set?top boxes, etc. ? offline adapters for notebooks ? telecom dc?dc converters ? all power supplies soic?8 d suffix case 751 marking diagrams pdip?7 p suffix case 626b p1216xxxx awl yywwg 1 xxxx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package pin connections 1 adj 8 hv 2 fb 3 cs 4 gnd 7 nc 6 v cc 5 drv see detailed ordering and shipping information in the ordering information section on page 16 of this data sheet. ordering information see detailed device marking information in the ordering information section on page 16 of this data sheet. device marking information http://onsemi.com 16xxx alyw 1 8 1 8
ncp1216, ncp1216a http://onsemi.com 2 universal input fosc = 35khz hv vcc drv gnd adj fb cs ncp1216 emi filter 1 2 3 45 6 7 8 r sense r comp + + + *see application section figure 1. typical application example pin function description pin no. pin name function pin description 1 adj adjust the skipping peak current this pin lets you adjust the level at which the cycle skipping process takes place. shorting this pin to ground, permanently disables the skip cycle feature. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 cs current sense input this pin senses the primary current and routes it to the internal comparator via an l.e.b. by inserting a resistor in series with the pin, you control the amount of ramp compensation you need. 4 gnd ic ground ? 5 drv driving pulses the driver?s output to an external mosfet. 6 v cc supplies the ic this pin is connected to an external bulk capacitor of typically 22 f. 7 nc ? this un?connected pin ensures adequate creepage distance. 8 hv generates the v cc from the line connected to the high?voltage rail, this pin injects a constant current into the v cc bulk capacitor.
ncp1216, ncp1216a http://onsemi.com 3 q set reset 1 v hv 1 2 3 4 5 6 7 8 drv gnd nc current sense adj fb skip cycle comparator 1.1 v overload? fault duration 20 k 19 k clock jittering 57 k 25 k 96 k 25 k 5 v figure 2. internal circuit architecture ? + ? + pull?up resistor uvlo high and low internal regulator hv current source q flip?flop d cmax = 75% reset 65 khz 100 khz 133khz ramp compensation ? + v ref 220 ns l.e.b 500 ma v cc internal v cc 1 ms ss* * available for ?a? version only. maximum ratings rating symbol value unit power supply voltage, v cc pin v cc 16 v maximum voltage on low power pins (except pin 8 and pin 6) ?0.3 to 10 v maximum voltage on pin 8 (hv), pin 6 (v cc ) decoupled to ground with 10 f 500 v maximum voltage on pin 8 (hv), pin 6 (v cc ) grounded 450 v minimum operating voltage on pin 8 (hv) 28 v maximum current into all pins except v cc (pin 6) and hv (pin 8) when 10 v esd diodes are activated 5.0 ma thermal resistance junction?to?air, pdip?7 version thermal resistance junction?to?air, soic?8 version r j?a r j?a 100 178 c/w maximum junction temperature t jmax 150 c temperature shutdown tsd 155 c hysteresis in shutdown 30 c storage temperature range ?60 to +150 c esd capability, hbm model (all pins except v cc and hv) 2.0 kv esd capability, machine model 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
ncp1216, ncp1216a http://onsemi.com 4 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, maximum t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic pin symbol min typ max unit dynamic self?supply v cc increasing level at which the current source turns off 6 vcc off 11.2 12.2 13.4 (note 1) v v cc decreasing level at which the current source turns on 6 vcc on 9.2 10.0 11.0 (note 1) v v cc decreasing level at which the latchoff phase ends 6 vcc latch 5.6 v internal ic consumption, no output load on pin 5, f sw = 65 khz 6 i cc1 990 1110 (note 2) a internal ic consumption, no output load on pin 5, f sw = 100 khz 6 i cc1 1025 1180 (note 2) a internal ic consumption, no output load on pin 5, f sw = 133 khz 6 i cc1 1060 1200 (note 2) a internal ic consumption, 1.0 nf output load on pin 5, f sw = 65 khz 6 i cc2 1.7 2.0 (note 2) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 100 khz 6 i cc2 2.1 2.4 (note 2) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 133 khz 6 i cc2 2.4 2.9 (note 2) ma internal ic consumption, latchoff phase, v cc = 6.0 v ncp1216 ncp1216a 6 i cc3 250 320 a internal startup current source (t j > 0 c) high?voltage current source, v cc = 10 v 8 ic1 4.9 (note 3) 8.0 11 ma high?voltage current source, v cc = 0 v 8 ic2 9.0 ma drive output output voltage rise?time @ c l = 1.0 nf, 10?90% of a 12 v output signal 5 t r 60 ns output voltage fall?time @ c l = 1.0 nf, 10?90% of a 12 v output signal 5 t f 20 ns source resistance 5 r oh 15 20 35 sink resistance 5 r ol 5.0 10 18 current comparator (pin 5 unloaded) input bias current @ 1.0 v input level on pin 3 3 i ib 0.02 a maximum internal current setpoint 3 i limit 0.93 1.08 1.14 v default internal current setpoint for skip cycle operation 3 i lskip 330 mv propagation delay from current detection to gate off state 3 t del 80 130 ns leading edge blanking duration 3 t leb 220 ns 1. v cc off and v cc on min?max always ensure an hysteresis of 2.0 v. 2. maximum value at t j = 0 c. 3. minimum value for t j = 125 c.
ncp1216, ncp1216a http://onsemi.com 5 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, maximum t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic pin symbol min typ max unit internal oscillator (v cc = 11 v, pin 5 loaded by 1.0 k ) oscillation frequency, 65 khz version f osc 58.5 65 71.5 khz oscillation frequency, 100 khz version f osc 90 100 110 khz oscillation frequency, 133 khz version f osc 120 133 146 khz built?in frequency jittering in percentage of f osc f jitter 4.0 % maximum duty?cycle ncp1216 ncp1216a d max 69 42 75 46.5 81 50 % feedback section (v cc = 11 v, pin 5 loaded by 1.0 k ) internal pullup resistor 2 r up 20 k pin 2 (fb) to internal current setpoint division ratio ? i ratio 3.3 skip cycle generation default skip mode level 1 v skip 0.9 1.1 1.26 v pin 1 internal output impedance 1 z out 25 k internal ramp compensation internal ramp level @ 25 c (note 4) 3 v ramp 2.6 2.9 3.2 v internal ramp resistance to c s pin 3 r ramp 19 k 4. a 1.0 m resistor is connected to the ground for the measurement.
ncp1216, ncp1216a http://onsemi.com 6 temperature ( c) figure 3. high voltage pin leakage current vs. temperature 0 10 20 30 40 50 ?25 0 25 50 75 100 125 hv pin leakage current @ 500 v ( a) figure 4. vcc off vs. temperature 11.0 11.5 12.0 12.5 13.0 13.5 14.0 ?25 0 25 50 75 100 12 5 temperature ( c) vcc off (v) figure 5. vcc on vs. temperature 9.0 9.5 10.0 10.5 11.0 11.5 12.0 ?25 0 25 50 75 100 125 vcc on (v) temperature ( c) 500 600 700 800 900 1000 1100 1200 1300 1400 ?25 0 25 50 75 100 12 5 temperature ( c) i cc1 ( a) figure 6. i cc1 (@ v cc = 11 v) vs. temperature 65 khz 133 khz 100 khz 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 ?25 0 25 50 75 100 125 temperature ( c) i cc2 (ma) 133 khz 100 khz 65 khz figure 7. i cc2 vs. temperature 50 70 90 110 130 150 ?25 0 25 50 75 100 12 5 133 khz 100 khz 65 khz f osc (khz) temperature ( c) figure 8. switching frequency vs. temperature typical characteristics
ncp1216, ncp1216a http://onsemi.com 7 5.30 5.40 5.50 5.60 5.70 5.80 5.90 ?25 0 25 50 75 100 125 temperature ( c) vcc latch (v) figure 9. vcc latch vs. temperature figure 10. i cc3 vs. temperature 0 100 200 300 400 ?25 0 25 50 75 100 12 5 temperature ( c) i cc3 ( a) 0 5 10 15 20 25 30 ?25 0 25 50 75 100 125 driver resistance ( ) temperature ( c) figure 11. drive sink and source resistance vs. temperature source sink 0.93 0.98 1.03 1.08 1.13 ?25 0 25 50 75 100 12 5 temperature ( c) current sense limit (v) figure 12. current sense limit vs. temperature ?25 0 25 50 75 100 125 1.00 1.05 1.10 1.15 1.20 temperature ( c) v skip (v) figure 13. v skip vs. temperature 72.0 72.5 73.0 73.5 74.0 74.5 75.0 ?25 0 25 50 75 100 12 5 temperature ( c) duty cycle (%) figure 14. ncp1216 max duty?cycle vs. temperature 50 150 250 350 ncp1216a ncp1216
ncp1216, ncp1216a http://onsemi.com 8 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 ?25 0 25 50 75 100 125 temperature ( c) v ramp (v) figure 15. ncp1216a max duty?cycle vs. temperature 2 4 6 8 10 12 14 ?25 0 25 50 75 100 125 ic1 (ma) temperature ( c) figure 16. v ramp vs. temperature figure 17. high voltage current source (@ v cc = 10 v) vs. temperature 45.0 45.5 46.0 46.5 47.0 48.5 49.0 ?25 0 25 50 75 100 125 temperature ( c) duty cycle (%) 47.5 48.0
ncp1216, ncp1216a http://onsemi.com 9 application information introduction the ncp1216 implements a standard current mode architecture where the switch?off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part count is the key parameter, particularly in low?cost ac?dc adapters, tv power supplies etc. due to its high?performance high?voltage technology, the ncp1216 incorporates all the necessary components normally needed in uc384x based supplies: timing components, feedback devices, low?pass filter and self?supply. this later point emphasizes the fact that on semiconductor?s ncp1216 does not need an auxiliary winding to operate: the product is naturally supplied from the high?voltage rail and delivers a v cc to the ic. this system is called the dynamic self?supply (dss): dynamic self?supply (dss): due to its very high voltage integrated circuit (vhvic) technology, on semiconductor?s ncp1216 allows for a direct pin connection to the high?voltage dc rail. a dynamic current source charges up a capacitor and thus provides a fully independent v cc level to the ncp1216. as a result, there is no need for an auxiliary winding whose management is always a problem in variable output voltage designs (e.g. battery chargers). adjustable skip cycle level: by offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. this point guarantees a noise?free operation with cheap transformers. skip cycle offers a proven mean to reduce the standby power in no or light loads situations. internal frequency dithering for improved emi signature: by modulating the internal switching frequency with the dss v cc ripple, natural energy spread appears and softens the controller?s emi signature. wide switching ? frequency offered with different options (65 khz ? 100 khz ? 133 khz): depending on the application, the designer can pick up the right device to help reducing magnetics or improve the emi signature before reaching the 150 khz starting point. ramp compensation: by inserting a resistor between the current sense (cs) pin and the actual sense resistor, it becomes possible to inject a given amount of ramp compensation since the internal sawtooth clock is routed to the cs pin. sub?harmonic oscillations in continuous conduction mode (ccm) can thus be compensated via a single resistor. over current protection (ocp): by continuously monitoring the fb line activity, ncp1216 enters burst mode as soon as the power supply undergoes an overload. the device enters a safe low power operation, which prevents from any lethal thermal runaway. as soon as the default disappears, the power supply resumes operation. unlike other controllers, overload detection is performed independently of any auxiliary winding level. in presence of a bad coupling between both power and auxiliary windings, the short circuit detection can be severely affected. the dss naturally shields you against these troubles. wide duty? cycle operation: wide mains operation requires a large duty?cycle excursion. the ncp1216 can go up to 75% typically. for continuous conduction mode (ccm) applications, the internal ramp compensation lets you fight against sub?harmonic oscillations. low standby power: if smps naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping unnecessary switching cycles, the ncp1216 drastically reduces the power wasted during light load conditions. in no?load conditions, the npc1216 allows the total standby power to easily reach next international energy agency (iea) recommendations. no acoustic noise while operating: instead of skipping cycles at high peak currents, the ncp1216 waits until the peak current demand falls below a user?adjustable 1/3 of the maximum limit. as a result, cycle skipping can take place without having a singing transformer, one can thus select cheap magnetic components free of noise problems. external mosfet connection: by leaving the external mosfet external to the ic, you can select avalanche proof devices, which in certain cases (e.g. low output powers), let you work without an active clamping network. also, by controlling the mosfet gate signal flow; you have an option to slow down the device commutation, therefore reducing the amount of electromagnetic interference (emi). spice model: a dedicated model to run transient cycle?by?cycle simulations is available but also an averaged version to help you closing the loop. ready?to?use templates can be downloaded in orcad?s pspice and intusoft?s isspice from on semiconductor web site, in the ncp1216 related section.
ncp1216, ncp1216a http://onsemi.com 10 dynamic self?supply the dss principle is based on the char ge/discharge of the v cc bulk capacitor from a low level up to a higher level. we can easily describe the current source operation with a bunch of simple logical equations: power?on: if v cc < vcc off then the current source is on, no output pulses if v cc decreasing > vcc on then the current source is off, output is pulsing if v cc increasing < vcc off then the current source is on, output is pulsing typical values are: vcc off = 12.2 v, vcc on = 10 v to better understand the operational principle, figure 18 offers the necessary light: 10 30 50 70 90 figure 18. the charge/discharge cycle over a 10 f v cc capacitor vcc off = 12.2 v vcc on = 10 v v ripple = 2.2 v on, i = 8 ma off, i = 0 ma output pulse the dss behavior actually depends on the internal ic consumption and the mosfet?s gate charge q g . if we select a 600 v 10 a mosfet featuring a 30 nc q g , then we can compute the resulting average consumption supported by the dss which is: i total f sw q g i cc1 . (eq. 1) the total ic heat dissipation incurred by the dss only is given by: i total v pin8 . (eq. 2) suppose that we select the ncp1216p065 with the above mosfet, the total current is (30 n 65 k) 900 2.9 ma. (eq. 3) supplied from a 350 vdc rail (250 vac), the heat dissipated by the circuit would then be: 350 v 2.9 ma 1w (eq. 4) as you can see, it exists a tradeoff where the dissipation capability of the ncp1216 fixes the maximum q g that the circuit can drive, keeping its dissipation below a given target. please see the ?power dissipation? section for a complete design example and discover how a resistor can help to heal the ncp1216 heat equation. application note and8069/d details tricks to widen the ncp1216 driving implementation, in particular for large q g mosfets. this document can be downloaded at www.onsemi.com/pub/collateral/and8069?d.pdf. ramp compensation ramp compensation is a known mean to cure sub?harmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty?cycle greater than 50%. to lower the current loop gain, one usually injects between 50% and 100% of the inductor down?slope. figure 19 depicts how internally the ramp is generated: cs l.e.b 19 k 2.9v 0v figure 19. inserting a resistor in series with the current sense information brings ramp compensation ? + from set?point r sense r comp dc max = 75 c in the ncp1216, the ramp features a swing of 2.9 v with a duty cycle max at 75%. over a 65 khz frequency, it corresponds to a 2.9 0.75 65 khz 251 mv s ramp. (eq. 5) in our flyback design, let?s suppose that our primary inductance l p is 350 h, delivering 12 v with a np : ns ratio of 1:0.1. the off time primary current slope is thus given by: v out v f l p n p n s 371 ma sor37mv s (eq. 6) when projected over an r sense of 0.1 , for instance. if we select 75% of the down?slope as the required amount of ramp compensation, then we shall inject 27 mv/ s. our internal compensation being of 251 mv/ s, the divider ratio (divratio) between r comp and the 19 k is 0.107. a few lines of algebra to determine r comp : 19 k divratio 1 divratio 2.37 k (eq. 7) frequency jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. ncp1216 of fers a 4% deviation of
ncp1216, ncp1216a http://onsemi.com 11 the nominal switching frequency whose sweep is synchronized with the v cc ripple. for instance, with a 2.2 v peak?to?peak ripple, the ncp1216p065 frequency will equal 65 khz in the middle of the ripple and will increase as v cc rises or decrease as v cc ramps down. figure 20 portrays the behavior we have adopted: figure 20. v cc ripple is used to introduce a frequency jittering on the internal oscillator sawtooth 65 khz 68 khz vcc off v cc ripple vcc on 62 khz skipping cycle mode the ncp1216 automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 2 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a determined level, the ic prevents the current from decreasing further down and starts to blank the output pulses: the ic enters the so?called skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches (figure 22). suppose we have the following component values: l p , primary inductance = 350 h f sw , switching frequency = 65 khz i p skip = 600 ma (or 333 mv / r sense ) the theoretical power transfer is therefore: 1 2 l p i p 2 f sw 4w. (eq. 8) if this ic enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 4 0.1 400 mw. (eq. 9) to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb level immediately gives the necessary insight: figure 21. 4.2 v, f b pin open 3.2 v, upper dynamic range normal current mode operation skip cycle operation i pmin = 333 mv / r sense fb 1 v when fb is above the skip cycle threshold (1.0 v by default), the peak current cannot exceed 1.0 v/r sense . when the ic enters the skip cycle mode, the peak current cannot go below v pin1 / 3.3. the user still has the flexibility to alter this 1.0 v by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. grounding pin 1 permanently invalidates the skip cycle operation. figure 22. output pulses at various power levels (x = 5 s/div) p1 < p2 < p3 power p1 power p2 power p3
ncp1216, ncp1216a http://onsemi.com 12 315.4u 882.7u 1.450m 2.017m 2.585m 300 200 100 0 figure 23. the skip cycle takes place at low peak currents which guarantees noise free operation skip cycle current limit max peak current non?latching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the adj pin 1 level, the output pulses are disabled as long as fb is pulled below pin 1. as soon as fb is relaxed, the ic resumes its operation. figure 24 depicts the application example: figure 24. another way of shutting down the ic without a definitive latchoff state 8 7 6 5 1 2 3 4 q1 on/off a full latching shutdown, including overtemperature protection, is described in application note and8069/d. power dissipation the ncp1216 is directly supplied from the dc rail through the internal dss circuitry. the current flowing through the dss is therefore the direct image of the ncp1216 current consumption. the total power dissipation can be evaluated using: (v hvdc 11 v) i cc2 (eq. 10) which is, as we saw, directly related to the mosfet q g . if we operate the device on a 90?250 vac rail, the maximum rectified voltage can go up to 350 vdc. however, as the characterization curves show, the current consumption drops at a higher junction temperature, which quickly occurs due to the dss operation. in our example, at t ambient = 50 c, i cc2 is measured to be 2.9 ma with a 10 a / 600 v mosfet. as a result, the ncp1216 will dissipate from a 250 vac network, 350 v 2.9 ma@t a 50 c 1w (eq. 11) the pdip?7 package of fers a junction?to?ambient thermal resistance r j?a of 100 c/w. adding some copper area around the pcb footprint will help decreasing this number: 12 mm x 12 mm to drop r j?a down to 75 c/w with 35 copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 copper thickness (2 oz.). for a soic?8, the original 178 c/w will drop to 100 c/w with the same amount of copper. w ith this later pdip?7 number, we can compute the maximum power dissipation that the package accepts at an ambient of 50 c: p max t jmax t amax r j a 1w (eq. 12) which barely matches our previous budget. several solutions exist to help improving the situation: 1. insert a resistor in series with pin 8: this resistor will take a part of the heat normally dissipated by the ncp1216. calculations of this resistor imply that v pin8 does not drop below 30 v in the lowest mains conditions. therefore, r drop can be selected with: r drop v bulkmin 50 v 8ma (eq. 13) in our case, v bulk minimum is 120 vdc, which leads to a dropping resistor of 8.7 k . with the above example in mind, the dss will exhibit a duty?cycle of: 2.9 ma 8ma 36% (eq. 14) by inserting the 8.7 k resistor, we drop 8.7 k *8ma 69.6 v (eq. 15) during the dss activation. the power dissipated by the ncp1216 is therefore: p instant *dss duty cycle (eq. 16) (350 69) * 8 m * 0.36 800 mw we can pass the limit and the resistor will dissipate (eq. 17) 1w 800 mw 200 mw or (eq. 18) p drop 69 2 8.7 k *0.36 2. select a mosfet with a lower q g : certain mosfets exhibit different total gate charges depending on the technology they use. careful selection of this component can help to significantly decrease the dissipated heat. 3. implement figure 3, from an8069/d, solution: this is another possible option to keep the dss functionality (good short?circuit protection and emi jittering) while driving any types of mosfets. this solution is recommended when the designer plans to use soic?8 controllers.
ncp1216, ncp1216a http://onsemi.com 13 4. connect an auxiliary winding: if the mains conditions are such that you simply can?t match the maximum power dissipation, then you need to connect an auxiliary winding to permanently disconnect the startup source. overload operation in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is interesting to implement a true short?circuit protection. a short?circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the fb pin level is pulled up to 4.2 v, as internally imposed by the ic. the peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated ef fects. please note that this can also happen in case of feedback loss, e.g. a broken optocoupler. to account for this situation, ncp1216 hosts a dedicated overload detection circuitry. once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty?cycle. the system auto?recovers when the fault condition disappears. during the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. this period of time depends on normal output load conditions and the maximum peak current allowed by the system. the time?out used by this ic works with the v cc decoupling capacitor: as soon as the v cc decreases from the vcc off level (typically 12.2 v) the device internally watches for an overload current situation. if this condition is still present when the vcc on level is reached, the controller stops the driving pulses, prevents the self?supply current source to restart and puts all the circuitry in standby, consuming as little as 350 a typical (i cc3 parameter). as a result, the v cc level slowly discharges toward 0 v. when this level crosses 5.6 v typical, the controller enters a new startup phase by turning the current source on: v cc rises toward 12.2 v and again delivers output pulses at the vcc off crossing point. if the fault condition has been removed before vcc on approaches, then the ic continues its normal operation. otherwise, a new fault cycle takes place. figure 25 shows the evolution of the signals in presence of a fault. figure 25. latchoff phase time time time fault is relaxed regulation occurs here v cc 12.2 v 10 v 5.6 v fault occurs here startup phase internal fault flag driver pulses drv driver pulses vcc off = 12.2 v vcc on = 10 v vcc latch = 5.6 v if the fault is relaxed during the v cc natural fall down sequence, the ic automatically resumes. if the fault still persists when v cc reached vcc on , then the controller cuts everything off until recovery. calculating the vcc capacitor as the above section describes, the fall down sequence depends upon the v cc level: how long does it take for the v cc line to go from 12.2 v to 10 v the required time depends on the startup sequence of your system, i.e. when you first apply the power to the ic. the corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12.2 v to 10 v, otherwise the supply will not properly start. the test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. let?s suppose that this time corresponds to 6ms. therefore a v cc fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. if the corresponding ic consumption, including
ncp1216, ncp1216a http://onsemi.com 14 the mosfet drive, establishes at 2.9 ma, we can calculate the required capacitor using the following formula: t vc i (eq. 19) with v = 2.2 v. then for a wanted t of 30 ms, c equals 39.5 f or a 68 f for a standard value (including 20% dispersions). when an overload condition occurs, the ic blocks its internal circuitry and its consumption drops to 350 a typical. this happens at v cc = 10 v and it remains stuck until v cc reaches 5.6 v: we are in latchoff phase. again, using the selected 68 f and 350 a current consumption, this latchoff phase lasts: 780 ms. protecting the controller against negative spikes as with any controller built upon a cmos technology, it is the designer?s duty to avoid the presence of negative spikes on sensitive pins. negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. sometimes, the injection can be so strong that internal parasitic scrs are triggered, engendering irremediable damages to the ic if a low impedance path is offered between v cc and gnd. if the current sense pin is often the seat of such spurious signals, the high?voltage pin can also be the source of problems in certain circumstances. during the turn?off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its v cc capacitor and keeps activating the mosfet on and off with a peak current limited by r sense . unfortunately, if the quality coefficient q of the resonating network formed by l p and c bulk is low (e.g. the mosfet r dson + r sense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. since we are talking about ms pulses, the amount of injected charge, (q = i * t), immediately latches the controller that brutally discharges its v cc capacitor. if this v cc capacitor is of suf ficient value, its stored energy damages the controller. figure 26 depicts a typical negative shot occurring on the hv pin where the brutal v cc discharge testifies for latchup. figure 26. a negative spike takes place on the bulk capacitor at the switch?off sequence v cc 5 v/div 10 ms/div v latch 1 v/div 0 simple and inexpensive cures exist to prevent from internal parasitic scr activation. one of them consists in inserting a resistor in series with the high?voltage pin to keep the negative current to the lowest when the bulk becomes negative (figure 27). please note that the negative spike is clamped to (?2 * v f ) due to the diode bridge. also, the power dissipation of this resistor is extremely small since it only heats up during the startup sequence. another option (figure 28) consists in wiring a diode from v cc to the bulk capacitor to force v cc to reach vcc on sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. for security reasons, two diodes can be connected in series.
ncp1216, ncp1216a http://onsemi.com 15 figure 27. figure 28. a simple resistor in series avoids any latchup in the controller or one diode forces v cc to reach v ccon sooner. d3 1n400 7 1 2 45 8 6 7 3 + + cv cc c bulk 1 2 45 8 6 7 3 + + cv cc c bulk r bulk > 4.7 k soft?start ? ncp1216a only the ncp1216a features an internal 1.0 ms soft?start activated during the power on sequence (pon). as soon as v cc reaches v ccoff , the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 v). this situation lasts during 1ms and further to that time period, the peak current limit is blocked to 1.0 v until the supply enters regulation. the soft?start is also activated during the over current burst (ocp) sequence. every restart attempt is followed by a soft?start activation. generally speaking, the soft?start will be activated when v cc ramps up either from zero (fresh power?on sequence) or 5.6 v, the latchoff voltage occurring during ocp. figure 29 portrays the soft?start behavior. the time scales are purposely shifted to offer a better zoom portion. figure 29. soft?start is activated during a startup sequence or an ocp condition
ncp1216, ncp1216a http://onsemi.com 16 ordering information device version marking package shipping ? NCP1216D65R2 65 khz 16d06 soic?8 2500 / tape & reel NCP1216D65R2g 65 khz 16d06 soic?8 (pb?free) 2500 / tape & reel ncp1216d100r2 100 khz 16d10 soic?8 2500 / tape & reel ncp1216d100r2g 100 khz 16d10 soic?8 (pb?free) 2500 / tape & reel ncp1216d133r2 133 khz 16d13 soic?8 2500 / tape & reel ncp1216d133r2g 133 khz 16d13 soic?8 (pb?free) 2500 / tape & reel ncp1216p65 65 khz p1216p065 pdip?7 50 units / rail ncp1216p65g 65 khz p1216p065 pdip?7 (pb?free) 50 units / rail ncp1216p100 100 khz p1216p100 pdip?7 50 units / rail ncp1216p100g 100 khz p1216p100 pdip?7 (pb?free) 50 units / rail ncp1216p133 133 khz p1216p133 pdip?7 50 units/ rail ncp1216p133g 133 khz p1216p133 pdip?7 (pb?free) 50 units/ rail ncp1216ad65r2 65 khz 16a06 soic?8 2500 / tape & reel ncp1216ad65r2g 65 khz 16a06 soic?8 (pb?free) 2500 / tape & reel ncp1216ad100r2 100 khz 16a10 soic?8 2500 / tape & reel ncp1216ad100r2g 100 khz 16a10 soic?8 (pb?free) 2500 / tape & reel ncp1216ad133r2 133 khz 16a13 soic?8 2500 / tape & reel ncp1216ad133r2g 133 khz 16a13 soic?8 (pb?free) 2500 / tape & reel ncp1216ap65 65 khz p1216ap06 pdip?7 50 units / rail ncp1216ap65g 65 khz p1216ap06 pdip?7 (pb?free) 50 units / rail ncp1216ap100 100 khz p1216ap10 pdip?7 50 units / rail ncp1216ap100g 100 khz p1216ap10 pdip?7 (pb?free) 50 units / rail ncp1216ap133 133 khz p1216ap13 pdip?7 50 units / rail ncp1216ap133g 133 khz p1216ap13 pdip?7 (pb?free) 50 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1216, ncp1216a http://onsemi.com 17 package dimensions soic?8 nb case 751?07 issue ah seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155
mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1216, ncp1216a http://onsemi.com 18 package dimensions pdip?7 p suffix case 626b?01 issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension l to center of lead when formed parallel. 4. package contour optional (round or square corners). 5. dimensions a and b are datums. 14 5 8 f note 2 ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max millimeters a 9.40 10.16 b 6.10 6.60 c 3.94 4.45 d 0.38 0.51 f 1.02 1.78 g 2.54 bsc h 0.76 1.27 j 0.20 0.30 k 2.92 3.43 l 7.62 bsc m ??? 10 n 0.76 1.01 a b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 ncp1216/d the product described herein (ncp1216), may be covered by the following u.s. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,70 9, 6,587,357. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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